UPD9971 datasheet(9/112 Pages) RENESAS

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µPD9971

Data Sheet S17455EJ2V0DS

6.14.1 AULDG2[1:0] ..................................................................................................................................... 63

6.14.2 AULDG1[5:0] ..................................................................................................................................... 63

6.15 Digital Volume (ASI Input R-ch) Setting for Audio DAC (AURDG)...........................................64

6.15.1 AURDG2[1:0]..................................................................................................................................... 64

6.15.2 AURDG1[5:0]..................................................................................................................................... 64

6.16 Setting of Analog Master Volume (L-ch) for Audio DAC (ADACLVR)......................................66

6.16.1 ADACLVRGA[4:0] .............................................................................................................................. 66

6.17 Setting of Analog Master Volume (R-ch) for Audio DAC (ADACRVR).....................................66

6.17.1 ADACRVRGA[4:0] ............................................................................................................................. 66

6.18 Setting of LSI Standby (MSIO) (STNBY2) ..................................................................................67

6.18.1 STMSO ............................................................................................................................................. 67

6.18.2 STMSI ............................................................................................................................................... 67

6.19 Setting of MSIO Mode (SEL_MSIO1)..........................................................................................67

6.19.1 SMBCLK............................................................................................................................................ 67

6.19.2 SMEN ................................................................................................................................................ 67

6.19.3 MMS .................................................................................................................................................. 68

6.19.4 MLOPSW .......................................................................................................................................... 68

6.19.5 MBF[2:0]............................................................................................................................................ 68

6.20 FS Switching and BCLK Switching in Audio Serial Interface (SEL_FS) ................................69

6.20.1 MCHI[3:0] .......................................................................................................................................... 69

6.20.2 MCHO[3:0] ........................................................................................................................................ 69

6.21 Setting of LSI Version (LSIVER) .................................................................................................70

6.21.1 VER[3:0] ............................................................................................................................................ 70

6.22 Setting of Bank in Serial Interface Mode (BANK) .....................................................................70

6.22.1 BANK[1:0].......................................................................................................................................... 70

7. POWER STARTUP PROCEDURE ........................................................................................................71

7.1 Wakeup Sequence .........................................................................................................................71

7.1.1 When a regulator is not used............................................................................................................... 71

7.1.2 When a regulator is used..................................................................................................................... 72

7.2 Shutdown Sequence .....................................................................................................................73

7.2.1 When a regulator is not used............................................................................................................... 73

7.2.2 When a regulator is used..................................................................................................................... 74

7.3 Power Saving Functions ...............................................................................................................75

7.3.1 Hardware power saving function ......................................................................................................... 75

7.3.2 Software power saving function........................................................................................................... 75

8. SETTING SEQUENCE............................................................................................................................76

8.1 Power Up Sequence ......................................................................................................................76

8.2 Basic Sequence for Switching Among Operation Modes .........................................................76

8.2.1 Mute setting......................................................................................................................................... 77

8.2.2 Standby setting/cancel ........................................................................................................................ 77

8.2.3 FS switching ........................................................................................................................................ 78

8.2.4 Path switching ..................................................................................................................................... 78

8.2.5 3DA/surround switching....................................................................................................................... 79

8.2.6 ASIO mode setting .............................................................................................................................. 79

8.3 Setting Sequence Examples.........................................................................................................80

8.3.1 Sound generator-DAC-line output (Clock: MCLK2 = 12 MHz) ............................................................. 81

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