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UPD9971 Datasheet(PDF) 64 Page - Renesas Technology Corp |
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UPD9971 Datasheet(HTML) 64 Page - Renesas Technology Corp |
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64 / 112 page ![]() µPD9971 Data Sheet S17455EJ2V0DS 62 Figure 6-1 Soft Mute Operation Soft mute ON Volume transition time Volume setting time = ∆G·tm/63 Mute Remark ∆G: Gain setting difference tm: Volume setting time Soft mute OFF 6.12 Digital Volume (Sound generator Output L-ch) Setting for Audio DAC (MELLDG) This register performs setting for digital gain (sound generator output L-ch). Address: 11H, register name: MELLDG, block: Digital volume, access: R/W, initial value: FFH D7 D6 D5 D4 D3 D2 D1 D0 MELLDG2[1:0] MELLDG1[5:0] 6.12.1 MELLDG2[1:0] Data Mode Initial Value Description MELLDG2[1:0] 11b Performs setting for digital gain (sound generator output L-ch) 6.12.2 MELLDG1[5:0] Data Mode Initial Value Description MELLDG1[5:0] 111111b Performs setting for digital gain (sound generator output L-ch) Remark The setting value is derived from the sum of the corresponding gain setting values in Digital gain settings 1 and 2 (Refer to Table 6-6 Digital Gain Settings 1, Table 6-7 Digital Gain Settings 2). |
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