UPD9971 datasheet(8/112 Pages) RENESAS

8 / 112 page

µPD9971

Data Sheet S17455EJ2V0DS

6.1.8 STREF.................................................................................................................................................50

6.2 Master Clock Switching (MCLK1A, MCLK1B, MCLK2A, and MCLK2B)................................... 51

6.2.1 MCLK1A[6:0] .......................................................................................................................................51

6.2.2 MLCK1B[7:0] .......................................................................................................................................51

6.2.3 MCLK2A[4:0] .......................................................................................................................................51

6.2.4 MCLK2B[7:0] .......................................................................................................................................51

6.3 Selecting Input Clock (MCLKSEL)............................................................................................... 52

6.3.1 MCLKSEL............................................................................................................................................52

6.3.2 CSTRTEN............................................................................................................................................52

6.4 FS Switching and BCLK Switching for ASIO (SEL_FS) ............................................................ 55

6.4.1 FS[2:0] .................................................................................................................................................55

6.4.2 BFS[4:0] ..............................................................................................................................................56

6.5 ASIO Mode Setting (SEL_ASI) ..................................................................................................... 57

6.5.1 EX3DAEN ............................................................................................................................................57

6.5.2 AULOOPSW ........................................................................................................................................57

6.5.3 SLR .....................................................................................................................................................57

6.5.4 AMS.....................................................................................................................................................57

6.5.5 ASIM....................................................................................................................................................57

6.5.6 LRCLK .................................................................................................................................................57

6.6 Digital Mixing Path (ASI Input Data) Selection (MIXING1) ........................................................ 58

6.6.1 DACLMIX[1:0] ......................................................................................................................................58

6.6.2 DACRMIX[1:0] .....................................................................................................................................58

6.6.3 DACLSW[1:0] ......................................................................................................................................58

6.6.4 DACRSW[1:0] ......................................................................................................................................58

6.7 Digital Mixing Path (Sound Generator Output Data) Selection (MIXING2).............................. 59

6.7.1 MELLMIX[1:0]......................................................................................................................................59

6.7.2 MELRMIX[1:0] .....................................................................................................................................59

6.7.3 MELLSW[1:0] ......................................................................................................................................59

6.7.4 MELRSW[1:0]......................................................................................................................................59

6.8 Digital Mixing Path (ASI to Sound Generator) Selection (MIXING3) ........................................ 60

6.8.1 PCMLSW.............................................................................................................................................60

6.8.2 PCMRSW ............................................................................................................................................60

6.9 VIB and LED Settings (LEDVIB) ................................................................................................... 60

6.9.1 VIB.......................................................................................................................................................60

6.9.2 LED .....................................................................................................................................................60

6.10 Setting of General-Purpose Output Pins (POUT) .................................................................... 61

6.10.1 POUT0 to POUT3..............................................................................................................................61

6.11 Audio Soft Mute Control (SMUTE)............................................................................................. 61

6.11.1 SLOPE[1:0]........................................................................................................................................61

6.11.2 AUSMUTE .........................................................................................................................................61

6.11.3 MELSMUTE.......................................................................................................................................61

6.12 Digital Volume (Sound generator Output L-ch) Setting for Audio DAC (MELLDG) .............. 62

6.12.1 MELLDG2[1:0]...................................................................................................................................62

6.12.2 MELLDG1[5:0]...................................................................................................................................62

6.13 Digital Volume (Sound generator Output R-ch) Setting for Audio DAC (MELRDG) ............. 63

6.13.1 MELRDG2[1:0] ..................................................................................................................................63

6.13.2 MELRDG1[5:0] ..................................................................................................................................63

6.14 Digital Volume (ASI Input L-ch) Setting for Audio DAC (AULDG)........................................... 63

UPD9971 Datasheet(PDF) 8 Page - Renesas Technology Corp

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