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UPD9971 Datasheet(PDF) 87 Page - Renesas Technology Corp

Part # UPD9971
Description  MOS INTEGRATED CIRCUIT
PDF  112 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

UPD9971 Datasheet(HTML) 87 Page - Renesas Technology Corp

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µPD9971
Data Sheet S17455EJ2V0DS
85
8.3.5 ASI-ASO output (Clock: MCLK = 12 MHz)
(1) Power on
Step
Item
Target registers, pins, etc.
1
Setting of regulator
REGUSE_B pin: Fixed to low (when regulator is used)
REGCNT pin: From low to high (when regulator is used)
2
Canceling hardware reset
RESET_B pin: From low to high
3
Setting of PLL (setting of CSTRT and MCLKSEL)
CSTRT pin, MCLKSEL, and CSTRTEN
(1 ms after setting of REGCNT when regulator is used)
4
Setting of PLL (input frequency)
MCLK1A = 4BH, MCLK1B = 9AH,
MCLK2A = 05H, MCLK2B = 2FH
5
Setting of sampling frequency
FS: 32 kHz, BFS: 64 fs
6
Setting of ASIO mode
MS, ASIM, LRCLK, SLR
7
Setting of soft mute
AUSMUTE = 0
8
Setting of path (digital mixing)
DACLSW: Through, DACRSW: Through
9
Canceling VREF standby
STREF = 1
10
Canceling PLL standby
STPLL1 = STPLL2 = 1 (5 ms after STREF standby is canceled)
11
Canceling function block standby
STSYNTH = STADIG = STADAC = STASI = STASO = 1
12
The internal clock is valid.
5 ms after STPLL1 and STPLL2 standby is canceled
(2) Transmitting music data
(3) Canceling mute
Step
Item
Target registers, pins, etc.
1
Canceling digital volume mute
AULDG, AURDG



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