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UPD9971 Datasheet(PDF) 23 Page - Renesas Technology Corp |
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UPD9971 Datasheet(HTML) 23 Page - Renesas Technology Corp |
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23 / 112 page  µPD9971 Data Sheet S17455EJ2V0DS 21 3. CPU INTERFACE Two interface modes are available: parallel interface mode, and serial interface mode. The access methods from the host CPU interface are described below. 3.1 Parallel Host CPU Interface Setting the PS pin to low level enters the parallel I/F mode. 3.1.1 Write access During write access, data is written to the µPD9971 from the system. • A0 is used to distinguish between address write cycles and data write cycles. • A1 is used to distinguish between register access for the sound generator and chip control. (0: For chip control, 1: For the sound generator) • In the address write cycle, the data write address is assigned to bits D7 to D0. Caution Be sure to fix the RD_B pin to the high level during address write cycles and data write cycles. Figure 3-1 Write Access (Single Access) CS_B A0, A1 WR_B RD_B D7 to D0 Address write cycle Data write cycle tsuAW thAW twWR trcWR tsuD1 thD1 Write address Write data D.C D.C H D.C Next address |
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