UPD9971 datasheet(72/112 Pages) RENESAS

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µPD9971

Data Sheet S17455EJ2V0DS

6.21 Setting of LSI Version (LSIVER)

This register shows the LSI version. This register is read only. It is impossible to write to the register.

Address: 3FH, register name: LSIVER, block: test, access: R, initial value: Undefined

VER[3:0]

6.21.1 VER[3:0]

Data

Mode

Initial Value

Description

VER [3:0]

Reads LSI version.

6.22 Setting of Bank in Serial Interface Mode (BANK)

This register performs setting for bank switching.

Address: 7CH, register name: BANK, block: CPU I/F, access: R/W, initial value: 00H

BANK[1:0]

6.22.1 BANK[1:0]

A1 Pin

Data

Initial Value

Description

00h

Accesses to addresses from 00H to 7FH of registers of Control

01h

Accesses to addresses from 80H to FFH of registers of Control

02h

Accesses to addresses from 00H to 7FH of sound generator

registers (in serial I/F).

03h

00H

Accesses to addresses from 80H to FFH of sound generator

registers (in serial I/F).

The bank switching in parallel interface mode is shown in the table below.

A1 Pin

Data

Initial Value

Description

Accesses to addresses from 00H to FFH of registers of Control

Accesses to addresses from 00H to FFH of sound generator

registers.

Caution

Be sure to set 0 for addresses from D7 to D2.

BANK switching is effective only in serial interface mode (PS = 1).

UPD9971 Datasheet(PDF) 72 Page - Renesas Technology Corp

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