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UPD9971 Datasheet(PDF) 97 Page - Renesas Technology Corp |
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UPD9971 Datasheet(HTML) 97 Page - Renesas Technology Corp |
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97 / 112 page  µPD9971 Data Sheet S17455EJ2V0DS 95 9.5.4 Serial CPU interface mode (Common to the 3-wire SPI mode and 4-wire SPI mode) Timing requirements (EVDD = 1.8 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit SCLK cycle timeperiod tckw 100 ns SCLK high level width tckh 50 ns SCLK low level width tckl 50 ns Data setup time tsck SCLK ↑ 20 ns Data hold time thck SCLK ↑ 10 ns SCS setup time tscs SCLK ↑ 20 ns SCS hold time thcs SCLK ↑ 20 ns Data delay time tracc Time until SCLK ↓ data is output 5 20 ns SCS recovery time tcsacc From SCS ↑ to SCS↓ 1 sclk Data delay time tdz Time until SCLK ↓ data change to Hi-z 0 20 ns SERINIT hold time thcsINIT SERINIT ↑ 80 ns SCS setup time tdhh SERINT ↑ 0 ns SERINIT width twhSERINIT 20 ns SCS hold time tdll SERINT ↓ 0 20 ns Serial interface write timing SCS SCLK Data R/W A0 D7 D0 tscs tckw thcs tckl tckh tsck thck Hi-Z Hi-Z Serial interface read timing SCS SCLK Data R/W A0 D7 D0 Hi-Z Hi-Z tscs tckw thcs tckl tckh tsck thck tdz Hi-Z tracc tracc |
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