UPD9971 datasheet(69/112 Pages) RENESAS

69 / 112 page

µPD9971

Data Sheet S17455EJ2V0DS

6.18 Setting of LSI Standby (MSIO) (STNBY2)

This register performs setting for standby.

MEN and MBCLK are set to standby only when both STMSI and STMSO bits are set to standby. For details, refer to

Table 2-3 Pin Statuses in MSIO Block.

Address: 20H, register name: STNBY2, block: MSIO, access: R/W, initial value: 00H

STMSI

STMSO

6.18.1 STMSO

Data

Mode

Initial Value

Description

Stand-by

Standby for MSO (external sound generator connection serial interface

input)

Normal operation

6.18.2 STMSI

Data

Mode

Initial Value

Description

Stand-by

Standby for MSO (external sound generator connection serial interface

input)

Normal operation

6.19 Setting of MSIO Mode (SEL_MSIO1)

This register performs setting for MSIO.

Address: 21H, register name: SEl_MSIO1, block: MSIO, access: R/W, initial value: 10H

MBFS[2:0]

MLOOPSW

MMS

SMEN

SMBCLK

6.19.1 SMBCLK

Data

Mode

Initial Value

Description

Normal

Sets bit clock MBCLK to normal.

Inverted

Sets bit clock MBCLK to invert.

6.19.2 SMEN

Data

Mode

Initial Value

Description

Frame

synchronization

mode

Sets MEN to frame synchronization mode.

Stereo mode

Sets MEN to LR stereo mode.

Remark

In LR stereo mode, R-ch data is stored in the high cycle of the MEN signal, and L-ch data in the Low

cycle.

UPD9971 Datasheet(PDF) 69 Page - Renesas Technology Corp

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