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UPD9971 Datasheet(PDF) 54 Page - Renesas Technology Corp |
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UPD9971 Datasheet(HTML) 54 Page - Renesas Technology Corp |
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54 / 112 page  µPD9971 Data Sheet S17455EJ2V0DS 52 6.3 Selecting Input Clock (MCLKSEL) This register selects the clock input pin. Address: 05H, register name: MCLKSEL, block: PLL, access: R/W, initial value: 00H D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 CSTRTEN MCLKSEL 6.3.1 MCLKSEL Be sure to leave the clock selection pin (CSTRT) open or fix it to the low level (a pull-down resister is contained) when clock input pins are switched by registers. Data Mode Initial Value Description 0 MCLK1 input Selects MCLK1 as the clock input pin. 1 MCLK2 input 0 Selects MCLK2 as the clock input pin. 6.3.2 CSTRTEN Use the MCLKSEL register for normal switching (In this case, the default setting is CSTRTEN = 0.). Data Mode Initial Value Description 0 CSTRT invalidation Uses the MCLKSEL register for switching clock input pins. 1 CSTRT validation 0 Uses the CSTRT pin for switching clock input pins. |
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