UPD9971 datasheet(53/112 Pages) RENESAS

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µPD9971

Data Sheet S17455EJ2V0DS

6.2 Master Clock Switching (MCLK1A, MCLK1B, MCLK2A, and MCLK2B)

These registers are for the settings for the master clocks, refer to 6.3.2 (2) Setting the master clock PLL2 for

Sound generators.

Address: 01H, register name: MCLK1A, block: PLL1, access: R/W, initial value: 1CH

MCLK1A[6:0]

Address: 02H, register name: MCLK1B, block: PLL1, access: R/W, initial value: 80H

MCLK1B[7:0]

Address: 03H, register name: MCLK2A, block: PLL2, access: R/W, initial value: 02H

MCLK2A[4:0]

Address: 04H, register name: MCLK2B, block: PLL2, access: R/W, initial value: 2AH

MCLK2B[7:0]

6.2.1 MCLK1A[6:0]

Data

Mode

Initial Value

Description

MCLK1A[6:0]

1Ch

Sets PLL1 used for generating the audio master clock.

6.2.2 MLCK1B[7:0]

Data

Mode

Initial Value

Description

MCLK1B[7:0]

80h

Sets PLL1 used for generating the audio master clock.

6.2.3 MCLK2A[4:0]

Data

Mode

Initial Value

Description

MCLK2A[4:0]

02h

Sets PLL2 used for generating the sound generator master clock.

6.2.4 MCLK2B[7:0]

Data

Mode

Initial Value

Description

MCLK2B[7:0]

2Ah

Sets PLL2 used for generating the sound generator master clock.

UPD9971 Datasheet(PDF) 53 Page - Renesas Technology Corp

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