UPD9971 datasheet(25/112 Pages) RENESAS

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µPD9971

Data Sheet S17455EJ2V0DS

3.1.2 Read access

During read access, data is read from the system by

µPD9971. The read access timing is shown below.

• A0 is used to distinguish between address write cycles and data read cycles.

• A1 is used to distinguish between register access for the sound generator and chip control

(0: For chip control ,1: For the sound generator)

• Operation is based on the detection of the rising edge of WR_B and RD_B by the system clock.

• In the address write cycle, the write data address is assigned to bits D7 to D0.

Figure 3-3 Read Access (Single Access)

CS_B

A0, A1

WR_B

RD_B

D7 to D0

Address write cycle

Data read cycle

Read address

Read data

D.C

Read data

thAR

tsuAR

twRD

trcRD

tdDO

taccDO

Figure 3-4 Read Access (Continuous Access)

CS_B

A0, A1

WR_B

RD_B

D7 to D0

Read access

Continuous read access

Read address

Read data

D.C

Read data

D.C

Read data

D.C

Remark

Set the CS_B pin to the low level during the read period. It is not necessary to always set the CS_B pin to

the low level during continuous read access.

D.C.: Don’t Care

UPD9971 Datasheet(PDF) 25 Page - Renesas Technology Corp

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