APEX20K datasheet(47/117 Pages) ALTERA

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Altera Corporation

APEX 20K Programmable Logic Device Family Data Sheet

APEX 20KE devices also support the MultiVolt I/O interface feature. The

APEX 20KE VCCINT pins must always be connected to a 1.8-V power

supply. With a 1.8-V VCCINT level, input pins are 1.8-V, 2.5-V, and 3.3-V

tolerant. The VCCIO pins can be connected to either a 1.8-V, 2.5-V, or 3.3-V

power supply, depending on the I/O standard requirements. When the

VCCIO

pins are connected to a 1.8-V power supply, the output levels are

compatible with 1.8-V systems. When VCCIO pins are connected to a 2.5-V

power supply, the output levels are compatible with 2.5-V systems. When

VCCIO

pins are connected to a 3.3-V power supply, the output high is

3.3 V and compatible with 3.3-V or 5.0-V systems. An APEX 20KE device

is 5.0-V tolerant with the addition of a resistor.

Table 13 summarizes APEX 20KE MultiVolt I/O support.

Notes to Table 13:

(1)

The PCI clamping diode must be disabled to drive an input with voltages higher than VCCIO, except for the 5.0-V

input case.

(2)

An APEX 20KE device can be made 5.0-V tolerant with the addition of an external resistor. You also need a PCI

clamp and series resistor.

(3)

When VCCIO = 3.3 V, an APEX 20KE device can drive a 2.5-V device with 3.3-V tolerant inputs.

ClockLock &

ClockBoost

Features

APEX 20K devices support the ClockLock and ClockBoost clock

management features, which are implemented with PLLs. The ClockLock

circuitry uses a synchronizing PLL that reduces the clock delay and skew

within a device. This reduction minimizes clock-to-output and setup

times while maintaining zero hold times. The ClockBoost circuitry, which

provides a clock multiplier, allows the designer to enhance device area

efficiency by sharing resources within the device. The ClockBoost

circuitry allows the designer to distribute a low-speed clock and multiply

that clock on-device. APEX 20K devices include a high-speed clock tree;

unlike ASICs, the user does not have to design and optimize the clock tree.

The ClockLock and ClockBoost features work in conjunction with the

APEX 20K device’s high-speed clock to provide significant improvements

in system performance and band-width. Devices with an X-suffix on the

ordering code include the ClockLock circuit.

The ClockLock and ClockBoost features in APEX 20K devices are enabled

through the Quartus II software. External devices are not required to use

these features.

Table 13. APEX 20KE MultiVolt I/O Support

Note (1)

VCCIO (V)

Input Signals (V)

Output Signals (V)

1.8

2.5

3.3

5.0

1.8

2.5

3.3

5.0

1.8

2.5

vvv

3.3

vvv

(2)

v(3)

APEX20K Datasheet(PDF) 47 Page - Altera Corporation

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