APEX20K datasheet(75/117 Pages) ALTERA

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Altera Corporation

APEX 20K Programmable Logic Device Family Data Sheet

Note to Table 36:

(1)

These parameters are worst-case values for typical applications. Post-compilation

timing simulation and timing analysis are required to determine actual worst-case

performance.

Tables 38 and 39 describe the APEX 20KE external timing parameters.

Table 36. APEX 20KE Routing Timing Microparameters

Note (1)

Symbol

Parameter

tF1-4

Fanout delay using Local Interconnect

tF5-20

Fanout delay estimate using MegaLab Interconnect

tF20+

Fanout delay estimate using FastTrack Interconnect

Table 37. APEX 20KE Functional Timing Microparameters

Symbol

Parameter

TCH

Minimum clock high time from clock pin

TCL

Minimum clock low time from clock pin

TCLRP

LE clear Pulse Width

TPREP

LE preset pulse width

TESBCH

Clock high time for ESB

TESBCL

Clock low time for ESB

TESBWP

Write pulse width

TESBRP

Read pulse width

Table 38. APEX 20KE External Timing Parameters

Note (1)

Symbol

Clock Parameter

Conditions

tINSU

Setup time with global clock at IOE input register

tINH

Hold time with global clock at IOE input register

tOUTCO

Clock-to-output delay with global clock at IOE output register

C1 = 10 pF

tINSUPLL

Setup time with PLL clock at IOE input register

tINHPLL

Hold time with PLL clock at IOE input register

tOUTCOPLL

Clock-to-output delay with PLL clock at IOE output register

C1 = 10 pF

APEX20K Datasheet(PDF) 75 Page - Altera Corporation

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