APEX20K datasheet(10/117 Pages) ALTERA

10 / 117 page

Altera Corporation

APEX 20K Programmable Logic Device Family Data Sheet

APEX 20K devices provide two dedicated clock pins and four dedicated

input pins that drive register control inputs. These signals ensure efficient

distribution of high-speed, low-skew control signals. These signals use

dedicated routing channels to provide short delays and low skews. Four

of the dedicated inputs drive four global signals. These four global signals

can also be driven by internal logic, providing an ideal solution for a clock

divider or internally generated asynchronous clear signals with high

fan-out. The dedicated clock pins featured on the APEX 20K devices can

also feed logic. The devices also feature ClockLock and ClockBoost clock

management circuitry. APEX 20KE devices provide two additional

dedicated clock pins, for a total of four dedicated clock pins.

MegaLAB Structure

APEX 20K devices are constructed from a series of MegaLABTM

structures. Each MegaLAB structure contains a group of logic array blocks

(LABs), one ESB, and a MegaLAB interconnect, which routes signals

within the MegaLAB structure. The EP20K30E device has 10 LABs,

EP20K60E through EP20K600E devices have 16 LABs, and the

EP20K1000E and EP20K1500E devices have 24 LABs. Signals are routed

between MegaLAB structures and I/O pins via the FastTrack

Interconnect. In addition, edge LABs can be driven by I/O pins through

the local interconnect. Figure 2 shows the MegaLAB structure.

Figure 2. MegaLAB Structure

ESB

MegaLAB Interconnect

Local

Interconnect

To Adjacent

LAB or IOEs

LABs

LE1

LE2

LE3

LE4

LE5

LE6

LE7

LE8

LE9

LE10

LE1

LE2

LE3

LE4

LE5

LE6

LE7

LE8

LE9

LE10

LE1

LE2

LE3

LE4

LE5

LE6

LE7

LE8

LE9

LE10

APEX20K Datasheet(PDF) 10 Page - Altera Corporation

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