APEX20K datasheet(52/117 Pages) ALTERA

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Altera Corporation

APEX 20K Programmable Logic Device Family Data Sheet

Notes to Table 16:

(1)

To implement the ClockLock and ClockBoost circuitry with the Quartus II software, designers must specify the

input frequency. The Quartus II software tunes the PLL in the ClockLock and ClockBoost circuitry to this frequency.

The fCLKDEV parameter specifies how much the incoming clock can differ from the specified frequency during

device operation. Simulation does not reflect this parameter.

(2)

Twenty-five thousand parts per million (PPM) equates to 2.5% of input clock period.

(3)

During device configuration, the ClockLock and ClockBoost circuitry is configured before the rest of the device. If

the incoming clock is supplied during configuration, the ClockLock and ClockBoost circuitry locks during

configuration because the tLOCK value is less than the time required for configuration.

(4)

The tJITTER specification is measured under long-term observation.

Tables 17 and 18 summarize the ClockLock and ClockBoost parameters

for APEX 20KE devices.

Table 17. APEX 20KE ClockLock & ClockBoost Parameters

Note (1)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Input rise time

5ns

Input fall time

5ns

tINDUTY

Input duty cycle

tINJITTER

Input jitter peak-to-peak

% of input

period

peak-to-

peak

tOUTJITTER

Jitter on ClockLock or ClockBoost-

generated clock

0.35

% of

output period

RMS

tOUTDUTY

Duty cycle for ClockLock or

ClockBoost-generated clock

tLOCK (2), (3)

Time required for ClockLock or

ClockBoost to acquire lock

µs

APEX20K Datasheet(PDF) 52 Page - Altera Corporation

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