ATAM894 datasheet(65/97 Pages) ATMEL

65 / 97 page

4679D–4BMCU–05/05

ATAM894

Figure 6-43.

Example of MCL Receive Dialog

6.3.4.6

8-bit Pseudo MCL Mode

In this mode, the SSI exhibits all the typical MCL operational features except for the acknowl-

edge-bit which is never expected or transmitted.

6.3.4.7

MCL Bus Protocol

The MCL protocol constitutes a simple 2-wire bi-directional communication highway via which

devices can communicate control and data information. Although the MCL protocol can support

multi-master bus configurations, the SSI in MCL mode is intended for use purely as a master

controller on a single master bus system. So all reference to multiple bus control and bus con-

tention will be omitted at this point.

All data is packaged into 8-bit telegrams plus a trailing handshaking or acknowledge-bit. Nor-

mally the communication channel is opened with a so-called start condition, which initializes all

devices connected to the bus. This is then followed by a data telegram, transmitted by the mas-

ter controller device. This telegram usually contains an 8-bit address code to activate a single

slave device connected onto the MCL bus. Each slave receives this address and compares it

with its own unique address. The addressed slave device, if ready to receive data, will respond

by pulling the SD line low during the 9th clock pulse. This represents a so-called MCL acknowl-

edge. The controller detecting this affirmative acknowledge then opens a connection to the

required slave. Data can then be passed back and forth by the master controller, each 8-bit tele-

gram being acknowledged by the respective recipient. The communication is finally closed by

the master device and the slave device put back into standby by applying a stop condition onto

the bus.

76 5 4321

7 6 54 3 210 A

msb

lsb

tx data 1

rx data 2

msb

lsb

Write STB

(tx data 1)

SRDY

ACT

Interrupt

(IFN = 0)

Interrupt

(IFN = 1)

Read SRB

(rx data 2)

SIR

SDD

Start

Stop

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