ATAM894 datasheet(71/97 Pages) ATMEL

71 / 97 page

4679D–4BMCU–05/05

ATAM894

6.3.4.16

Serial Receive Buffer (SRB) – Byte Read

The SRB is the receive buffer of the SSI. The shift register clocks serial data in (most significant

bit first) and the loads content into the receive buffer when the complete telegram has been

received.

6.3.5

Combination Modes

The UTCM consists of two timers (Timer 2 and Timer 3) and a serial interface. There is a multi-

tude of modes in which the timers and serial interface can work together.

The 8-bit wide serial interface operates as shift register for modulation and demodulation. The

modulator and demodulator units work together with the timers and shift the data bits into or out

of the shift register.

6.3.5.1

Combination Mode Timer 2 and SSI

Figure 6-48.

Combination Timer 2 and SSI

Primary register address: '9'hex

First read cycle

Bit 7

Bit 6

Bit 5

Bit 4

Reset value: xxxxb

Second read cycle

Bit 3

Bit 2

Bit 1

Bit 0

Reset value: xxxxb

4-bit Counter 2/1

RES

OVF1

Compare 2/1

T2CO1

POUT

CL2/2

DCG

T2M1

P4CR

8-bit Counter 2/2

RES

OVF2

Compare 2/2

T2CO2

T2CM

Timer 2 - control

TOG2

INT4

Bi-phase

Manchester

modulator

OUTPUT

MOUT

T2O

Timer 2

modulator

output-stage

T2M2

Control

T2C

CL2/1

T2I

SYSCL

T1OUT

TOG3

SCL

I/O-bus

8-bit shift register

MSB

LSB

Shift_CL

SIC1

SIC2

SISC

SCLI

Control

STB

SRB

Output

INT3

I/O-bus

SSI-control

TOG2

POUT

T1OUT

SYSCL

MCL_SC

MCL_SD

Transmit

buffer

Receive

buffer

CM1

I/O-bus

POUT

SCL

DCGO

TOG2

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