ATAM894 datasheet(56/97 Pages) ATMEL

56 / 97 page

4679D–4BMCU–05/05

ATAM894

Note:

1. In this mode, the SSI can be used only as demodulator (8-bit NRZ rising edge). All other SSI

modes are not allowed.

6.3.3.8

Timer 3 Control Register 1 (T3C) Write

6.3.3.9

Timer 3 Status Register 1 (T3ST) Read

Note:

The status bits T3C1, T3C2 and T3ED will be reset after a READ access to T3ST.

0110

Manchester demodulation/pulse-width demodulation(1)

(T2O -> T3O)

0101

Biphase demodulation (T2O -> T3O)

0100

Timer/counter with external capture mode (T3I)

0011

Not allowed

0010

Not allowed

0001

Not allowed

0000

Not allowed

Table 6-13.

Timer 3 Mode Select Bits (Continued)

Mode

T3M3

T3M2

T3M1

T3M0

Timer 3 Modes

Primary register address: 'C'hex — Write

Bit 3Bit 2Bit 1

Bit 0

Write

T3EIM

T3TOP

T3TS

T3R

Reset value: 0000b

T3EIM

Timer 3 Edge Interrupt Mask

T3EIM = 0, disables the interrupt when an edge event for Timer 3 occurs (T3I)

T3EIM = 1, enables the interrupt when an edge event for Timer 3 occurs (T3I)

T3TOP

Timer 3 Toggle Output Preset

T3TOP = 0, sets toggle output (M3) to '0'

............. ...... T3TOP = 1, sets toggle output (M3) to '1'

............. ...... Note: If T3R = 1, no output preset is possible

T3TS

Timer 3 Toggle with Start . T3TS = 0, Timer 3 output is not toggled during the start

...... ...... T3TS = 1, Timer 3 output is toggled if started with T3R

T3R

Timer 3 Run

...... ...... T3R = 0, Timer 3 stop and reset

...... ...... T3R = 1, Timer 3 run

Primary register address: 'C'hex — Read

Bit 3Bit 2Bit 1

Bit 0

Read

- - -

T3ED

T3C2

T3C1

Reset value: x000b

T3ED

Timer 3 Edge Detect

This bit will be set by the edge-detect logic of Timer 3 input (T3I)

T3C2

Timer 3 Compare 2

This bit will be set when a match occurs between Counter 3 and T3CO2

T3C1

Timer 3 Compare 1

This bit will be set when a match occurs between Counter 3 and T3CO1

ATAM894 Datasheet(PDF) 56 Page - ATMEL Corporation

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