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ATAM894 Datasheet(PDF) 83 Page - ATMEL Corporation |
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ATAM894 Datasheet(HTML) 83 Page - ATMEL Corporation |
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83 / 97 page  83 4679D–4BMCU–05/05 ATAM894 Figure 6-65. FSK Modulation 7. Data EEPROM The internal data EEPROM offers 2 pages of 512 bits each. Both pages are organized as 32 × 16 bit words. The programming voltage as well as the write cycle timing is generated on chip. If it is necessary to be compatible with the ROM parts, only the default page must be used with the flash part. Also for compatibility reasons the access to the EEPROM is handled via the MCL (serial interface) as in the corresponding ROM parts. The page select is performed by either writing ''01h'' (page 1) or ''09h'' (page 0) to the EEPROM. Figure 7-1. Block Diagram EEPROM 0 1 2 3 4 0 12 34 01 2 3 Counter 3 CM31 CM32 SO 40 1 2 01 2 0 1 2 0 1 2 0 1 2 01 20 1 20 1 2 3 T3R 40 T3O 1 01 0 16-bit read/write buffer Address control 8-bit data register EEPROM 2 x 32 x 16 HV-generator Timing control Mode control I/O control SCL V DD SDA Page 1 Page 0 --> write "01h" --> write "09h" V SS |
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