ATAM894 datasheet(47/97 Pages) ATMEL

47 / 97 page

4679D–4BMCU–05/05

ATAM894

6.3.3

Timer 3

6.3.3.1

Features

• Two Compare Registers

• Capture Register

• Edge Sensitive Input with Zero Cross Detection Capability

• Trigger and Single Action Modes

• Output Control Modes

• Automatic Modulation and Demodulation Modes

• FSK Modulation

• Pulse width Modulation (PWM)

• Manchester Demodulation Together with SSI

• Bi-phase Demodulation Together with SSI

• Pulse-width Demodulation Together with SSI

Figure 6-24.

Timer 3

Timer 3 consists of an 8-bit up-counter with two compare registers and one capture register. The

timer can be used as event counter, timer and signal generator. Its output can be programmed

as modulator and demodulator for the serial interface. The two compare registers enable various

modes of signal generation, modulation and demodulation. The counter can be driven by inter-

nal and external clock sources. For external clock sources, it has a programmable edge-

sensitive input which can be used as counter input, capture signal input or trigger input. This

timer input is synchronized with SYSCL. Therefore, in the power-down mode SLEEP (CPU core

→sleep and OSC-Stop →yes), this timer input is stopped too. The counter is readable via its

capture register while it is running. In capture mode, the counter value can be captured by a pro-

grammable capture event from the Timer 3 input or Timer 2 output.

8-bit Counter 3

RES

Compare 3/1

T3CO1

T3CP

T3CO2

Control

T3O

CL3

T3I

T3EX

SYSCL

T1OUT

POUT

I/O-bus

Compare 3/2

T3CM1

T3CM2

T3C

T3ST

Modulator 3

Demodu-

lator 3

Control

TOG3

INT5

RES

CM31

T3I

T3EX

TOG2

SCI

T3M

T3CS

I/O-bus

Timer 2

SSI

CP3

ATAM894 Datasheet(PDF) 47 Page - ATMEL Corporation

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