ATAM894 datasheet(33/97 Pages) ATMEL

33 / 97 page

4679D–4BMCU–05/05

ATAM894

Figure 6-9.

Timer 1 and Watchdog

6.3.1.1

Timer 1 Control Register 1 (T1C1)

Note:

* Bit 3 = MSB, Bit 0 = LSB

The three bits T1C[2:0] select the divider for timer 1. The resulting time interval depends on this

divider and the timer 1 input clock source. The timer input can be supplied by the system clock,

the 32-kHz oscillator or via the clock management. If the clock management generates the

SUBCL, the selected input clock from the RC-oscillator, 4-MHz oscillator or an external clock is

divided by 16.

Q1 Q2

Q3 Q4

Q11

Q14

RES

Decoder

Watchdog

mode control

MUX for interval timer

Decoder

MUX for watchdog timer

T1RM T1C2 T1C1

T1C0

WDL

WDR WDT1 WDT0

WDC

RES

T1MUX

SUBCL

T1BP T1IM

T1IM=0

T1IM=1

INT2

T1OUT

T1C2

RESET

(NRST)

Watchdog

Divider/8

Divider

RESET

T1C1

Write of the

T1C1 register

CL1

WDCL

Read of the

CWD register

Address: '7'hex — Subaddress: '8'hex

Bit 3*

Bit 2

Bit 1

Bit 0

T1C1

T1RM

T1C2

T1C1

T1C0

Reset value: 1111b

T1RM

Timer 1 Restart Mode

T1RM = 0, write access without Timer 1 restart

T1RM = 1, write access with Timer 1 restart

Note: if WDL = 0, Timer 1 restart is impossible

T1C2

Timer 1 Control bit 2

T1C1

Timer 1 Control bit 1

T1C0

Timer 1 Control bit 0

ATAM894 Datasheet(PDF) 33 Page - ATMEL Corporation

ATAM894 Datasheet(HTML) 33 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97

Datasheet Download

Link URL