ATAM894 datasheet(52/97 Pages) ATMEL

52 / 97 page

4679D–4BMCU–05/05

ATAM894

Timer 3 – Mode 8: FSK Modulation with Shift Register Data (SO)

The two compare registers are used for generating two different time intervals. The SSI internal

data output (SO) selects which compare register is used for the output frequency generation. A

'0' level at the SSI data output enables the compare register 1. A '1' level enables compare reg-

ister 2. The compare- and compare mode registers must be programmed to generate the two

frequencies via the output toggle flip-flop. The SSI can be supplied with the toggle signal of

Timer 2. The Timer 3 counter is driven by an internal or external clock source. The Timer 2

counter is driven by the Counter 3 (TOG3) (see section “Combination Mode 13”).

Figure 6-31.

FSK Modulation

Timer 3 – Mode 9: Pulse-width Modulation with the Shift Register

The two compare registers are used for generating two different time intervals. The SSI internal

data output (SO) selects which compare register is used for the output pulse generation. In this

mode both compare- and compare mode registers must be programmed for generating the two

pulse widths. It is also useful to enable the single-action mode for extreme duty-cycles. Timer 2

is used as baud-rate generator and for the trigger restart of Timer 3. The SSI must be supplied

with a toggle signal of Timer 2. The counter is driven by an internal or external clock source (see

section “Combination Mode 7”).

Figure 6-32.

Pulse-width Modulation

012340 1 23401 2 3

Counter 3

CM31

CM32

40 1 2 0 12012 0 120 1 201201 20 1 2 3

T3R

T3O

0 0 00 00 00 0

0 0 0 0

Counter 3

CM31

CM32

T3O

00 00 0 1 2 3 4 5 6 7 8 9101112131415 0 12 3 4 5

TOG2

67 8

1112

2 3

SIR

SCO

T3R

ATAM894 Datasheet(PDF) 52 Page - ATMEL Corporation

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