ATAM894 datasheet(43/97 Pages) ATMEL

43 / 97 page

4679D–4BMCU–05/05

ATAM894

6.3.2.5

Timer 2 Registers

Timer 2 has 6 control registers to configure the timer mode, the time interval, the input clock and

its output function. All registers are indirectly addressed using extended addressing as

described in section ”Addressing Peripherals” on page 22. The alternate functions of the Ports

BP41 or BP42 must be selected with the Port 4 control register P4CR, if one of the Timer 2

modes require an input at T2I/BP41 or an output at T2O/BP42.

6.3.2.6

Timer 2 Control Register (T2C)

6.3.2.7

Timer 2 Mode Register 1 (T2M1)

Address: '7'hex — Subaddress: '0'hex

Bit 3Bit 2Bit 1Bit 0

T2C

T2CS1

T2CS0

T2TS

T2R

Reset value: 0000b

T2CS1

Timer 2 Clock Select bit 1

T2CS0

Timer 2 Clock Select bit 0

T2TS

Timer 2 Toggle with Start

T2TS = 0, the output flip-flop of Timer 2 is not toggled with the timer start

T2TS = 1, the output flip-flop of Timer 2 is toggled when the timer is started with T2R

T2R

Timer 2 Run

T2R = 0, Timer 2 stop and reset

T2R = 1, Timer 2 run

Table 6-8.

Timer 2 Clock Select Bits

T2CS1

T2CS0

Input Clock (CL 2/1) of Counter Stage 2/1

System clock (SYSCL)

Output signal of Timer 1 (T1OUT)

Internal shift clock of SSI (SCL)

Reserved

Address: '7'hex — Subaddress: '1'hex

Bit 3

Bit 2

Bit 1

Bit 0

T2M1

T2D1

T2D0

T2MS1

T2MS0

Reset value: 1111b

T2D1

Timer 2 Duty cycle bit 1

T2D0

Timer 2 Duty cycle bit 0

T2MS1

Timer 2 Mode Select bit 1

T2MS0

Timer 2 Mode Select bit 0

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