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PM3350-SW Datasheet(PDF) 153 Page - PMC-Sierra, Inc |
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PM3350-SW Datasheet(HTML) 153 Page - PMC-Sierra, Inc |
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153 / 224 page ![]() ELAN 8X10 PM3350 ELAN 8 X10 DATA SHEET PMC-970109 ISSUE 3 8 PORT ETHERNET SWITCH PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND PMC-SIERRA, INC. CUSTOMERS ONLY 151 specified local memory address. Contact PMC-Sierra applications support for additional information, if required. Register 0x04: Command/Status Bit Type Function Default Bit 31 R/W DPE 0 Bit 30 R/W SSE 0 Bit 29 R/W RMA 0 Bit 28 R/W RTA 0 Bit 27 R/W STA 0 Bit 26 R DVtim[1] 0 Bit 25 R DVtim[0] 1 Bit 24 R/W DPR 0 Bit 23 R FBCap 1 Bit 22 t o 16 R Reserved 0x00 Bit 15 to 10 R Reserved 0x00 Bit 9 R/W FBen 0 Bit 8 R/W SEen 0 Bit 7 R Wcyc 0 Bit 6 R/W PEen 0 Bit 5 R VPs 0 Bit 4 R MWIen 0 Bit 3 R SCen 0 Bit 2 R/W Men 0 Bit 1 R/W MSen 0 Bit 0 R ISen 0 The lower 16 bits of this register make up the Command register which provides basic control over the PM3350's ability to respond to PCI accesses. When a 0 is written to all bits in the command register, the PM3350 is logically disconnected from the PCI bus for all accesses except configuration accesses. The upper 16-bits are used to record status information for PCI bus related events. Reads to the status portion of this register behave normally. Writes are slightly different in that bits can be reset, but not set. A bit is reset whenever the register is written, and the data in the corresponding bit location is a 1. ISen: The I/O Space Enable (ISen) bit is hardwired to zero as the PM3350 does not implement I/O space. |
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