PM3350-SW datasheet(156/224 Pages) PMC

156 / 224 page

ELAN 8X10

PM3350 ELAN 8 X10

DATA SHEET

PMC-970109

ISSUE 3

8 PORT ETHERNET SWITCH

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND PMC-SIERRA, INC. CUSTOMERS ONLY

154

sub-class of the device and CCODE[7:0] specify a register specific

programming interface.

Note:

Base Class Code:

0x02

Network Controller

Sub-Class Code:

0x00

Ethernet Network Controller

None defined.

Bit

Type

Function

Default

Bit 31 to 24

BIST[7:0]

0x00

Bit 23 to 16

HDTYPE[7:0]

0x00

Bit 15 to 8

R/W

LT[7:0]

0x00 or 0x20

Bit 7 to 0

R/W

CLSIZE[7:0]

0x00

CLSIZE[7:0]:

The Cache Line Size (CLSIZE[7:0]) bits specify the size of the system

cacheline in units of dwords. The PM3350 is not capable of generating the

Memory Write and Invalidate command so this register is hardwired to zeros.

LT[7:0]:

The Latency Timer (LT[7:0]) bits specify, in units of the PCI clock, the value

of the Latency Timer for the PM3350. The value of the LT is application

specific and should be set appropriately by the PCI BIOS at system

initialization.

The default value depends on the PCIRUN bit value set by the state on the

MDATA[31] pin when RST* is de-asserted. If the PCIRUN bit defaults to a

logic 0, the reset the value of LT[7:0] is zero. If the PCIRUN bit defaults to a

logic 1, the reset the value of LT[7:0] is decimal 32.

HDTYPE[6:0]:

The Header Type (HDTYPE[7:0]) bits specify the layout of the first 64 bytes

of the configuration space. Only the 0x00 encoding is supported.

BIST[7:0]:

Built In Self Test (BIST) is not implemented so the register is hardwired to

zero.

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