PM3350-SW datasheet(158/224 Pages) PMC

158 / 224 page

ELAN 8X10

PM3350 ELAN 8 X10

DATA SHEET

PMC-970109

ISSUE 3

8 PORT ETHERNET SWITCH

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND PMC-SIERRA, INC. CUSTOMERS ONLY

156

After determining the memory requirements of the PM3350 resources, the

PCI Host can map them to its desired location by modifying the

MemBase[27:20] bits.

The default value depends on the PCIRUN bit value set by the state on the

MDATA[31] pin when RST* is de-asserted. If the PCIRUN bit defaults to a

logic 0, the reset the value of MemBase[27:20] is zero. If the PCIRUN bit

defaults to a logic 1, the reset the value of MemBase[27:20] becomes the

zero extended value of MDATA[25:22] (CHIPID[3:0).

Bit

Type

Function

Default

Bit 31 to 0

XROMBase[31:0]

0x00000000

XROMBase[31:0]:

The PM3350 does not contain an expansion ROM; therefore, this register is

hardwired to zeros.

Bit

Type

Function

Default

Bit 31 to 24

MAX_LAT[7:0]

0x00

Bit 23 to 16

MIN_GNT[7:0]

0x03

Bit 15 to 8

INTPIN[7:0]

0x01

Bit 7 to 0

R/W

INTLNE[7:0]

0x00

INTLNE[7:0]:

The Interrupt Line (INTLNE[7:0]) field is used to indicate interrupt line routing

information. The values in this register are system specific and set by the

PCI Host.

INTPIN[7:0]:

The Interrupt Pin (INTPIN[7:0]) field is used to specify the interrupt pin the

PM3350 uses. Because the PM3350 will use INTA* on the PCI bus, the

value in this register is set to one.

MIN_GNT[7:0]:

The Minimum Grant (MIN_GNT[7:0]) field specifies how long of a burst

period the bus master needs. The PM3350 has a minimum grant of 750 ns

(25 cycles). This register always returns 0x03.

MAX_LAT[7:0]:

The Maximum Latency (MAX_LAT[7:0]) field specifies how often a bus

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