PM3350-SW datasheet(154/224 Pages) PMC

154 / 224 page

ELAN 8X10

PM3350 ELAN 8 X10

DATA SHEET

PMC-970109

ISSUE 3

8 PORT ETHERNET SWITCH

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND PMC-SIERRA, INC. CUSTOMERS ONLY

152

MSen:

When the Memory Space Enable (MSen) bit is set to one, the PM3350 will

respond to PCI bus memory accesses. Clearing MSen disables memory

accesses.

Men:

When the Master Enable (Men) bit is set to one, the PM3350 can act as an

master. Clearing Men disables the PM3350 from generating PCI accesses.

SCen:

The PM3350 does not decode PCI special cycles. The SCen bit is hardwired

to 0.

MWIen:

The PM3350 does not generate memory-write-and-invalidate commands.

The MWIen bit is hardwired to 0.

VPs:

The PM3350 is not a VGA device. The VPs bit is hardwired to 0.

PEen:

When the PEen bit is set to one, the PM3350 can report parity errors.

Clearing the PEen bit causes the PM3350 to ignore parity errors.

Wcyc:

The PM3350 does not perform address and data stepping. The Wcyc bit is

hardwired to 0.

SEen:

When the SEen bit is set high, address parity errors result in the assertion of

the SERR* output. Clearing the SEen bit disables the SERR* output. SEen

and PEen must be set to report an address parity error.

FBen:

If the fast back-to-back enable (FBen) bit is set, the PM3350 bus master will

attempt to do fast back-to-back cycles across the targets.

FBCap:

The Fast Back-to-Back Capable (FBCap) bit is hardwired to one to indicate

the PM3350 supports fast back-to-back transactions with other targets.

DPR:

The Data Parity Reported (DPR) bit is set high if the PM3350 has monitored

or reported a data parity error to one of its transactions as a bus master and

the PEen bit is set. The DPR bit is cleared by the PCI Host.

PM3350-SW Datasheet(PDF) 154 Page - PMC-Sierra, Inc

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