PM3350-SW datasheet(155/224 Pages) PMC

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ELAN 8X10

PM3350 ELAN 8 X10

DATA SHEET

PMC-970109

ISSUE 3

8 PORT ETHERNET SWITCH

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND PMC-SIERRA, INC. CUSTOMERS ONLY

153

DVtim[1:0]:

The DEVSEL Timing (DVtim) bits specify the allowable timings for the

assertion of DEVSEL* by the PM3350 as a target. These bits are hardwired

to zeros as the PM3350 asserts DEVSEL using fast (1-cycle) response

timing.

STA:

The Signaled Target Abort (STA) bit is hardwired to zero because the

PM3350 will never generate a Target Abort during a slave access cycle.

RTA:

The Received Target Abort (RTA) bit is set high by the PM3350 when as an

initiator, its transaction is terminated by a target abort. The RTA bit is cleared

by the PCI Host.

RMA:

The Received Master Abort (RMA) bit is set high by the PM3350 when as an

initiator, its transaction is terminated by a master abort. The RMA bit is

cleared by the PCI Host.

SSE:

The Signaled System Error (SSE) bit is set high when ever the PM3350

asserts the SERR* output. The SSE bit is cleared by the PCI Host.

DPE:

The Data Parity Error (DPE) bit is set high when ever the PM3350 detects a

parity error, even if parity error handling is disabled by clearing PEen in the

Command register. The DPE bit is cleared by the PCI Host.

Bit

Type

Function

Default

Bit 31 to 24

CCODE[23:16]

0x02

Bit 23 to 16

CCODE[15:8]

0x00

Bit 15 to 8

CCODE[7:0]

0x00

Bit 7 to 0

REVID[7:0]

0x01

REVID[7:0]:

The Revision Identifier (REVID[7:0]) bits specify a device specific revision

identifier and are chosen by PMC-Sierra.

CCODE[23:0]:

The class code (CCODE[23:0]) bits are divided into three groupings:

CCODE[23:16] define the base class of the device, CCODE[15:8] define the

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