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PM7375-SC Datasheet(PDF) 170 Page - PMC-Sierra, Inc

Part # PM7375-SC
Description  LOCAL ATM SAR & PHYSICAL LAYER
PDF  430 Pages
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Manufacturer  PMC [PMC-Sierra, Inc]
Direct Link  http://www.pmc-sierra.com
Logo PMC - PMC-Sierra, Inc

PM7375-SC Datasheet(HTML) 170 Page - PMC-Sierra, Inc

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PM7375 LASAR-155
DATA SHEET
PMC-931127
ISSUE 6
LOCAL ATM SAR & PHYSICAL LAYER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
154
10.1.54
Register 0x52 (0x148): RACP Match Header Pattern
Bit
Type
Function
Default
Bit 15
Unused
X
Bit 14
Unused
X
Bit 13
Unused
X
Bit 12
Unused
X
Bit 11
Unused
X
Bit 10
Unused
X
Bit 9
Unused
X
Bit 8
Unused
X
Bit 7
R/W
GFC[3]
0
Bit 6
R/W
GFC[2]
0
Bit 5
R/W
GFC[1]
0
Bit 4
R/W
GFC[0]
0
Bit 3
R/W
PTI[2]
0
Bit 2
R/W
PTI[1]
0
Bit 1
R/W
PTI[0]
0
Bit 0
R/W
CLP
0
CLP:
The CLP bit contains the pattern to match in the eighth bit of the fourth octet of
the 53 octet cell, in conjunction with the RACP Match Header Mask Register.
The PASS bit in the RACP Control/Status Register must be set to logic zero to
enable dropping of cells matching this pattern.
PTI[2:0]:
The PTI[2:0] bits contain the pattern to match in the fifth, sixth and seventh bits
of the fourth octet of the 53 octet cell, in conjunction with the RACP Match
Header Mask Register. The PASS bit in the RACP Control/Status Register must
be set to logic zero to enable dropping of cells matching this pattern.
GFC[3:0]:
The GFC[3:0] bits contain the pattern to match in the first, second, third and
fourth bits of the first octet of the 53 octet cell, in conjunction with the RACP
Match Header Mask Register. The PASS bit in the RACP Control/Status Register
must be set to logic zero to enable dropping of cells matching this pattern. Note
that an all zeros pattern must be present in the VPI and VCI fields of the idle or
unassigned cell.



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