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PM7375-SC Datasheet(PDF) 167 Page - PMC-Sierra, Inc |
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PM7375-SC Datasheet(HTML) 167 Page - PMC-Sierra, Inc |
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167 / 430 page ![]() PM7375 LASAR-155 DATA SHEET PMC-931127 ISSUE 6 LOCAL ATM SAR & PHYSICAL LAYER PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 151 HECPASS: The HECPASS bit controls the dropping of cells based on the detection of an uncorrectable HEC error. When HECPASS is a logic zero, cells containing an uncorrectable HEC error are dropped. When HECPASS is a logic one, cells are passed to the RALP block regardless of errors detected in the HEC. In addition, the HEC verification finite state machine never exits in the correction mode. Regardless of the programming of this bit, cells are always dropped while the cell delineation state machine is in the 'HUNT' or 'PRESYNC' states. DISCOR: The DISCOR bit disables the HEC error correction algorithm. When DISCOR is a logic zero, the error correction algorithm is enabled, and single bit errors detected in the cell header are corrected. When DISCOR is a logic one, the error correction algorithm is disabled, and any error detected in the cell header is treated as an uncorrectable HEC error. PASS: The PASS bit controls the function of the cell filter. When PASS is written with a logic zero, all cells matching the cell filter are dropped. When PASS is a logic one, the match header pattern registers are ignored and filtering of cells with VPI and VCI fields set to 0 is not performed. The default state of this bit together with the default states of the bits in the RACP Match Mask and RACP Match Pattern Registers enable the dropping of cells containing all zero VCI and VPI fields. OCDV: The OCDV bit indicates the cell delineation state. When OCDV is set high, the cell delineation state machine is in the 'HUNT' or 'PRESYNC' states, and is hunting for the cell boundaries in the synchronous payload envelope. When OCDV is set low, the cell delineation state machine is in the 'SYNC' state and cells are passed to the RALP block. Reserved: The reserved bit must be programmed to logic zero for proper operation. |
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