TMPR3911 datasheet(227/462 Pages) TOSHIBA

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Chapter 9 I/O Module

9-9

9.3

I/O Registers

9.3.1

I/O Control Register

OFFSET

= $180:

Bit

Label

RESET

Read/Write

Reserved

31-24

IODEBSEL[6:0]

R/W

Reserved

22-16

IODIREC[6:0]

R/W

Reserved

14-8

IODOUT[6:0]

R/W

Reserved

6-0

IODIN[6:0]

–

IODEBSEL[6:0]:

These bits select the debounce mode for the 7 general purpose I/O pins. Setting a specific bit

location to a logic “1” causes the respective general purpose I/O port signal to be filtered by a

debounce circuit for the input signal direction. Clearing a specific bit location to a logic “0” causes

the respective general purpose I/O port signal to bypass the input debounce circuit.

IODIREC[6:0]:

These bits control the direction of the 7 general purpose I/O pins. Setting a specific bit location

to a logic “1” configures the respective general purpose I/O pin to be an output. Clearing a specific

bit location to a logic “0” configures the respective general purpose I/O pin to be an input.

IODOUT[6:0]:

These bits correspond to the data output values for the 7 general purpose I/O pins. Setting or

clearing a specific bit location controls the logic state of the respective general purpose I/O pin, if

that pin is configured as an output.

IODIN[6:0]:

read-only

These bits correspond to the data input values for the 7 general purpose I/O pins. Reading a

specific bit location returns the logic state of the respective general purpose I/O pin, regardless of

whether that pin is configured as an output or input.

TMPR3911 Datasheet(PDF) 227 Page - Toshiba Semiconductor

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