TMPR3911 datasheet(229/462 Pages) TOSHIBA

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Chapter 9 I/O Module

9-11

9.3.5

MFIO Select Register

OFFSET

= $190:

Bit

Label

RESET

Read/Write

31-0

MFIOSEL[31:0]

$F20F0FFF

R/W

MFIOSEL[31:0]:

These bits correspond to the select mode for the 32 multi-function I/O pins. Setting a specific bit

location to a logic “1” configures the respective multi-function I/O pin to be selected as a bi-

directional I/O port. Clearing a specific bit location to a logic “0” configures the respective multi-

function I/O pin to be selected as a standard/normal pin function.

9.3.6

I/O Power-Down Register

OFFSET

= $194:

Bit

Label

RESET

Read/Write

31-7

Reserved

6-0

IOPD[6:0]

$7F

R/W

IOPD[6:0]:

These bits control the power-down state for the 7 general purpose I/O pins. Setting a specific bit

location to a logic “1” configures the respective general purpose I/O pin to power down when the

TMPR3911/12 powers down. Clearing a specific bit location to a logic “0” configures the

respective general purpose I/O pin to be in an active state at all times.

9.3.7

MFIO Power-Down Register

OFFSET

= $198:

Bit

Label

RESET

Read/Write

31-0

MFIOPD[31:0]

$FAF03FFC

R/W

MFIOPD[31:0]:

These bits control the power-down state for the 32 multi-function I/O ports. Setting a specific bit

location to a logic “1” configures the respective multi-function I/O port to power down when the

TMPR3911/12 powers down. Clearing a specific bit location to a logic “0” configures the

respective multi-function I/O port to be in an active state at all times.

TMPR3911 Datasheet(PDF) 229 Page - Toshiba Semiconductor

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