TMPR3911 datasheet(233/462 Pages) TOSHIBA

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Chapter 10 IR Module

10-3

10.2.4

Functional Description

The Consumer IR logic remains idle until the CPU activates the IR logic by writing to the IR Control

1 Register to enable the Consumer mode (ENCONSM

= “1”). Prior to enabling the Consumer mode, the

CPU must configure the Baud Value (BAUDVAL), Period Value (PER), and OnTime Value (ONTIME)

fields located in the IR Control 2 Register. BAUDVAL[7:0] is used to pre-scale IR master clock

(IRCLK) (since typical consumer IR data rates are in the kHz range instead of the MHz range).

PER[7:0] is used to define the period of the pulses for a burst, representing the number of pre-scaled

counts per period. ONTIME[7:0] defines the amount of time that the pulse is on for the given period,

representing the number of pre-scaled counts for which the pulse is on. ONTIME should always be less

than PER or the IROUT signal will never transition low.

Transmit data = number of pulse and no-pulse width are written by the CPU into a 16-bit holding

reaches zero, it will load the lower 7 bits of the holding register’s upper byte into the Period Number

Counter and the upper bit into the 1-bit ON/OFF Register.

If the upper bit is set to a “1” then the IROUT signal will be a “1” until the OnTime Width Counter

reaches it’s terminal count. The OnTime Width Counter freezes once it reaches it’s terminal count in

order to prevent the signal from transitioning until the counter is loaded again. The IROUT signal will

continue to transition according to the Period Value and OnTime Value until the 7-bit Period Number

Counter reaches zero. At this time the lower 7 bits of the holding register’s lower byte is loaded into the

Period Number Counter and the upper bit of the lower byte is loaded into the 1-bit ON/OFF Register. If

the upper bit is set to a “0” this time, then the IROUT signal will remain low for as many period counts

as are defined by the value loaded into the 7-bit Period Number Counter. Thus the CPU controls the

pulse generation by defining a number of pulses to burst (upper bit set to “1”, lower 7-bit data defines

the number of pulses) or an amount of time when there are no pulses (upper bit set to “0”, lower 7-bit

data defines the number of pulse times when IROUT is “0”) on a byte by byte basis. The OnTime Value

and Period Value timing relationships are shown in Figure 10.2.3.

Period

On Time

TXHOLD Upper Bit = “0”

TXHOLD Upper Bit = “1”

Period = (PER+1)

× (BAUDVAL+1) ×

fIRCLK

On Time = ONTIME

× (BAUDVAL+1) ×

fIRCLK

Figure 10.2.3 Consumer IR Signal Generation

10.2.5

Related Interrupts

IRCONSMINT:

Whenever the upper byte of data is loaded into the 7-bit Period Number Counter, the lower byte

of data is loaded into an intermediate holding register. At this time the 16-bit IR Holding Register

is empty. The IRCONSMINT interrupt is then set to inform the CPU that the IR Holding Register

is available. The CPU must fill the next word of data into the IR Holding Register before the 7-bit

Period Number Counter is finished counting the periods for both the upper and lower bytes of data.

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