TMPR3911 datasheet(246/462 Pages) TOSHIBA

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Chapter 11 Magicbus Module

11-6

The transmit clock rate is also programmable, using the Magicbus Baud Rate Generator. The

Magicbus specification supports data rates from 250 kbps to 14.75 Mbps. See Section 11.3.4 for a

detailed description of the Magicbus Baud Rate Generator.

As mentioned previously, the transmit data consists of 16-bit or 32-bit groups. Seamless operation is

possible, whereby each data bit for each group is transmitted in a continuous and non-interrupted

fashion. This seamless operation results in the fastest possible data rate for Magicbus. In order to

maintain seamless operation, the Transmit Holding Register must be reloaded before the contents of the

Transmit Shift Register have been completely shifted out.

In order to accommodate slower peripherals which cannot keep up with fast Magicbus data rates, the

Magicbus Module contains a programmable Inter-Packet Delay Counter. This counter allows the

insertion of a programmable number of baud clocks of delay between bytes, words, or longs of the data

stream, as shown in Figure 11.3.3. See Section 11.3.4 for a detailed description of the Inter-Packet

Delay Counter.

INTER-PACKET

DELAY

Figure 11.3.3 Magicbus Inter-Packet Delay

11.3.3

Receiver

The Magicbus Receiver consists of a Shift Register and Holding Register which support the receiving

of serial data from attached Magicbus peripheral devices to the Magicbus Module. Data from the

MBUSDATA input port is shifted in serially to the 32-bit Receive Shift Register. The receive clock

from the MBUSCLK port is used to clock the serial data through the Receive Shift Register. This allows

a peripheral to control the data rate of the Magicbus Receiver (allowing support for slower peripherals),

since the receiver uses the peripheral’s transmit clock as it’s clock source. When the Magicbus Module

is configured for long mode (LONG

= “1”), all 32 bits of the Receive Shift Register are valid. When the

Magicbus Module is configured for word mode (LONG

= “0”), only the first 16 bits of the Receive

Shift Register are valid.

The contents of the Receive Shift Register are then fed in parallel to the 32-bit Receive Holding

or 32 bits of data depending on the selected mode.

The Receive Holding Register is read by either the DMA circuit or directly by the CPU. The

Magicbus Module provides an interrupt (MBUSRXBUFAVAILINT) whenever the Receive Holding

(LONG

= “1”), all 32 bits of the Receive Holding Register are valid. When the Magicbus Module is

configured for word mode (LONG

= “0”), only the lower 16 bits of the Receive Holding Register are

valid.

The Magicbus Module issues an interrupt (MBUSRXERRINT) if the Receive Holding Register is

loaded twice from the Receive Shift Register before the MBUSRXBUFAVAILINT interrupt is serviced

and the data in the Receive Holding Register was never read. This situation might occur if the DMA

circuit or the CPU cannot keep up with the incoming data rate of the Magicbus port.

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