TMPR3911 datasheet(247/462 Pages) TOSHIBA

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Chapter 11 Magicbus Module

11-7

11.3.4

Control Logic

The Magicbus Module contains several sets of counters which are used to generate the various

internal control signals and clocks needed for the transmitter and receiver sections. A block diagram of

the control logic is shown in Figure 11.3.4.

The ENMBUS control bit is used to enable the Magicbus Module by triggering the On/Off Logic

circuit. When the ENMBUS control bit is deasserted to disable the Magicbus Module, the module will

not shutdown until the Transmit Holding Register and Transmit Shift Register are empty plus a couple

of Magicbus baud clocks of delay. This allows the Magicbus Module to cleanly complete any pending

transactions before shutdown of the module. The MBUSON status bit indicates whether the Magicbus

Module is still enabled or not.

The programmable Magicbus Baud Rate Generator provides variable control of the transmit clock

rate, as determined by the BAUDRATE[7:0] control register value preloaded into the Baud Rate

Generator. The output of the Baud Rate Generator is the Magicbus baud clock, which is used to operate

the Transmit Shift Register and provides the MBUSCLK whenever TMPR3911/12 is configured as the

Magicbus bus master. The Magicbus specification supports data rates from 250 kbps to 14.75 Mbps. As

mentioned previously, the Magicbus Module supports 4 different combinations of clock polarity and

phase, as determined by the CLKPOL and PHAPOL control bits. The Magicbus specification specifies

the use of only one of these combinations: CLKPOL

= “0” and PHAPOL = “1”, which means that

MBUSDATA is always pushed on the rising edge of MBUSCLK and always sampled on the falling

edge of MBUSCLK.

The Magicbus Transmitter control logic consists of a Transmit Bit Counter and a programmable

Transmit Inter-Packet Delay Counter. The Transmit Bit Counter is used to count the number of bits to

be shifted out the Transmit Shift Register. This counter operates as a divide-by-16 (for word mode) or a

divide-by-32 (for long mode), and is also used to generate the load pulse for transferring the contents of

the Transmit Holding Register to the Transmit Shift Register.

Depending on the configuration of the ENBYTEWAIT and ENWORDWAIT control bits, the

Transmit Bit Counter will also trigger the counting of the Transmit Inter-Packet Delay Counter, which is

used in order to accommodate slower peripherals which cannot keep up with fast Magicbus data rates.

This counter allows the insertion of a programmable number of baud clocks of delay (based on the

DELAYVAL[7:0] control register value) between either bytes, words, or longs. Delay is always inserted

after each long (32-bit) group of bits, but is only inserted between bytes or words if the respective wait

enable control bits (ENBYTEWAIT and ENWORDWAIT) are asserted. In addition, if no delay is

desired, then the DELAYVAL[7:0] register value should be set to “0”.

TMPR3911 Datasheet(PDF) 247 Page - Toshiba Semiconductor