TMPR3911 datasheet(249/462 Pages) TOSHIBA

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Chapter 11 Magicbus Module

11-9

11.3.5

DMA Address Generation

The Magicbus Module provides support for both transmit and receive DMA. Since the Magicbus

Module operates half-duplex, a single DMA channel is shared between transmit or receive, with only

one direction using the buffer at a given time. The circuit used to generate the DMA address, as well as

half-buffer and end-of-buffer interrupts is shown in Figure 11.3.5.

The DMA buffer size is programmable (up to a maximum of 1 MByte) and the buffer start address is

also programmable (anywhere over the full 32-bit address space). The DMA buffer can be configured in

a circular buffer mode or a one-time buffer mode, depending on the configuration of the ENDMALOOP

control bit. For the circular mode, the DMA address is continuously incremented (each time a DMA

acknowledge is received from the TMPR3911/12’s central DMA controller) and rolls over back to the

start address after the end-of-buffer is reached and will continue operating in a continuous and circular

manner. For the one-time mode, the DMA logic will stop executing whenever the end-of-buffer is

reached.

Half-buffer and end-of-buffer DMA address counter interrupts are available, allowing the CPU to

minimize overhead and utilize the DMA buffer in a ping-pong fashion. For transmit mode, the CPU can

use these interrupts to fill or write one half of the buffer while the other half is being emptied by the

DMA controller for transmitting Magicbus data. Similarly, for receive mode, the CPU can use these

interrupts to empty or read one half of the buffer while the other half is being filled by the DMA

controller from received Magicbus data.

Also available is a direct CPU read/write mode for bypassing the DMA, allowing the CPU to read or

write the Magicbus data on a word by word (or long by long) basis, if so desired. Separate DMA

enables are provided for receive and transmit.

The DMA circuit also provides the DMA pointer status value, which is the actual 18-bit DMA

address counter output. This value indicates exactly where the current address is pointing to in the

overall DMA buffer, and is available via reading of the DMACNT[19:2] status register bits.

END-OF-BUFFER

INTERRUPT

CNT

LOAD

LOGIC

DMA

STARTVAL

CNTL

PEG

CONTROL FROM CPU

MBUS

CNTL 1

PEG

DMA

LENGTH

CNTL

PEG

CMP

ADDR CNT

DMA COUNT

DMA ADDR

HALF-BUFFER

INTERRUPT

ONE-TIME VS.

CIRCULAR MODE

÷2

CMP

Figure 11.3.5 Magicbus DMA Address Generation

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