TMPR3911 datasheet(245/462 Pages) TOSHIBA

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Chapter 11 Magicbus Module

11-5

11.3.2

Transmitter

The Magicbus Transmitter consists of a Holding Register and Shift Register which support the serial

data transmission from the Magicbus Module to attached Magicbus peripheral devices. The 32-bit

Transmit Holding Register is loaded with parallel data from either the DMA circuit or directly from the

CPU. The Magicbus Module provides an interrupt (MBUSTXBUFAVAILINT) whenever the ENMBUS

control bit is enabled or when the Transmit Holding Register is available (i.e., empty). When the

Magicbus Module is configured for long mode (LONG

= “1”), all 32 bits of the Transmit Holding

= “0”), only the

lower 16 bits of the Transmit Holding Register are valid.

The Magicbus Transmit Holding Register can be accessed at one of 2 address locations. One location

corresponds to Normal Mode and the other location corresponds to Swap Mode. As mentioned

previously, the Swap Mode is used for transferring Command Words, for which the clock and data

signals are swapped.

The contents of the Transmit Holding Register then feed the 32-bit Transmit Shift Register. This data

is transferred in parallel whenever the Transmit Shift Register is empty and available. The Magicbus

Module provides an interrupt (MBUSEMPTYINT) whenever the Transmit Holding Register and

Transmit Shift Register are both available (i.e., empty).

The Magicbus Module also issues an interrupt (MBUSTXERRINT) if the Transmit Holding Register

is written to when the Holding Register is not available (i.e., not empty). In this case, not enough time

was provided for the contents of the Transmit Holding Register to be transferred to the Transmit Shift

The contents of the Transmit Shift Register are then shifted out serially to the MBUSDATA output

port (except for Command Words which use Swap Mode). When the Magicbus Module is configured

for long mode (LONG

= “1”), all 32 bits of the Transmit Shift Register are valid. When the Magicbus

Module is configured for word mode (LONG

= “0”), only the first 16 bits of the Transmit Shift Register

are valid.

The Magicbus Module supports 4 different combinations of clock polarity and phase, as determined

by the CLKPOL and PHAPOL control bits. Figure 11.3.2 shows a timing diagram of the clock and data

relationships for these 4 combinations. This flexibility allows data to be pushed and sampled on either

the rising or falling edges of the clock. However, the actual Magicbus protocol and specification

specifies the use of only one of these combinations: CLKPOL

= “0” and PHAPOL = “1”, which means

that MBUSDATA is always pushed on the rising edge of MBUSCLK and always sampled on the falling

edge of MBUSCLK.

MBUSCLK

CLKPOL = 1 PHAPOL = 1

CLKPOL = 0 PHAPOL = 1

CLKPOL = 1 PHAPOL = 0

CLKPOL = 0 PHAPOL = 0

MBUSDATA

Figure 11.3.2 Magicbus Clock and Data Relationships

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