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TMPR3911 Datasheet(PDF) 248 Page - Toshiba Semiconductor |
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TMPR3911 Datasheet(HTML) 248 Page - Toshiba Semiconductor |
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248 / 462 page  Chapter 11 Magicbus Module 11-8 ÷16/÷32 RX BIT COUNTER CMD WORD DET LOGIC RX BUFFER STATUS LOGIC DECODE RX CNT LOAD LOGIC DECODE ÷16/÷32 TX BIT COUNTER ENBYTEWAIT ENWORDWAIT PRGM TX INTER- PACKET DELAY COUNTER TX BUFF AVAILABLE INT TX ERROR INT TX BUFF EMPTY INT RX BUFF AVAILABLE INT RX HOLD LOAD CMD WORD DETECT INT BAUD CLOCK WORD VS. LONG WORD VS. LONG 6 8 5 TX BUFFER STATUS LOGIC DELAY LOAD LOGIC DMA LOGIC ON/OFF LOGIC RX ERROR INT TX CLOCK SWAP CONTROL SHUTDOWN TX SHIFT LOAD MBUS DMA REQ MBUSON BAUDRATE[7:0] DELAYVAL[7:0] RX CLOCK ENMBUS PRGM BAUD RATE GEN Figure 11.3.4 Magicbus Control Logic The Magicbus Receiver control logic consists of a Receive Bit Counter and a circuit for detecting the receipt of a Command Word, whereby the clock and data signal functions are swapped. The Magicbus Receiver circuitry (including the Receive Bit Counter and the Receive Shift Register) uses the receive clock from the MBUSCLK port. This allows a peripheral to control the data rate of the Magicbus Receiver (allowing support for slower peripherals), since the receiver uses the peripheral’s transmit clock as it’s clock source. The Receive Bit Counter is used to count the number of bits to be shifted into the Receive Shift Register. This counter operates as a divide-by-16 (for word mode) or a divide-by-32 (for long mode), and is also used to generate the load pulse for transferring the contents of the Receive Shift Register to the Receive Holding Register. The Command Word detect logic monitors the MBUSCLK and MBUSDATA input lines and generates an interrupt (MBUSDETINT) whenever a Command Word is detected. |
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