TMPR3911 datasheet(253/462 Pages) TOSHIBA

253 / 462 page

Chapter 11 Magicbus Module

11-13

PHAPOL:

Setting this bit will cause the Magicbus Transmitter to clock data out on the rising edge of

MBUSCLK to be sampled by the peripherals on the falling edge of MBUSCLK.

CLKPOL:

Setting this bit will invert the MBUSCLK pin.

SLAVE:

Setting this bit will cause the MBUSCLK and MBUSDATA pins to be inputs and will enable the

Magicbus Receiver circuit. The transition from master to slave will not take place until the

Magicbus Transmit Holding Register and Transmit Shift Register are empty.

FSLAVE:

Setting this bit forces Slave Mode without regard to the status of the Magicbus Transmit Holding

LONG:

Setting this bit will cause the Magicbus Transmitter and Magicbus Receiver to handle 32 bits per

buffer. Otherwise 16 bits is assumed. This bit must be set for DMA transactions.

ENMBUS:

Setting this bit will enable the Magicbus Module. When this bit is cleared the Magicbus Module

is kept in a reset state. But clearing this bit gives no effect on the Magicbus Control Register. This

bit should not be set until all other control bits are setup.

11.4.2

Magicbus Control 2 Register

OFFSET

= $0E4:

write-only

Bit

Label

RESET

Read/Write

31-24

DELAYVAL[7:0]

23-16

BAUDRATE[7:0]

15-0

Reserved

DELAYVAL[7:0]:

write-only

These bits define the number of Magicbus baud clocks of delay to insert between either bytes,

words, or longs. Delay is always inserted after a long, but is only inserted between bytes or words

if the respective enables (ENBYTEWAIT or ENWORDWAIT) are set. If no delay is desired then

the register should be set to zero.

BAUDRATE[7:0]:

write-only

These bits define the baudrate of the Magicbus Transmitter. The following equation determines

the baudrate (fMBUSMCLK is the frequency of the Magicbus master clock.):

baudrate

= fMBUSMCLK ÷ (BAUDRATE[7:0] ∗2 + 2)

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