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TMPR3911 Datasheet(PDF) 255 Page - Toshiba Semiconductor |
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TMPR3911 Datasheet(HTML) 255 Page - Toshiba Semiconductor |
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255 / 462 page  Chapter 11 Magicbus Module 11-15 11.4.6 Magicbus Transmit Holding Register OFFSET = $0F8: Normal write-only OFFSET = $0F4: Swap write-only Bit Label RESET Read/Write 31-0 TXDATA[31:0] X W TXDATA[31:0]: write-only These bits are the data to be transmitted. This register should only be loaded after the MBUSTXBUFAVAILINT interrupt is set. Writing to the Swap location will cause the clock and data lines to be swapped for this character of data. For word mode, only bits 15:0 are valid. 11.4.7 Magicbus Receive Holding Register OFFSET = $0F8: read-only Bit Label RESET Read/Write 31-0 RXDATA[31:0] X R RXDATA[31:0]: read-only These bits are the receive data. The bits are valid after the MBUSRXBUFAVAILINT interrupt is set. For word mode, only bits 15:0 are valid. |
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