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WM8991 Datasheet(PDF) 101 Page - Wolfson Microelectronics plc

Part # WM8991
Description  Mobile Multimedia CODEC with Dual-Mode Class AB/D Speaker Driver
PDF  174 Pages
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Manufacturer  WOLFSON [Wolfson Microelectronics plc]
Direct Link  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM8991 Datasheet(HTML) 101 Page - Wolfson Microelectronics plc

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Pre-Production
WM8991
w
PP, May 2008, Rev 3.1
101
DIGITAL AUDIO INTERFACE
The digital audio interface is used for inputting DAC data to the WM8991 and outputting ADC data
from it. It uses five pins:
•
ADCDAT: ADC data output
•
ADCLRC: ADC data alignment clock (An inverted ADCLRC is also available via GPIO)
•
DACDAT: DAC data input (An alternative DACDAT is also available via GPIO)
•
DACLRC: DAC data alignment clock (An alternative DACLRC is also available via GPIO)
•
BCLK: Bit clock, for synchronisation (An alternative BCLK is also available via GPIO)
The clock signals BCLK, ADCLRC and DACLRC can be outputs when the WM8991 operates as a
master, or inputs when it is a slave (see Master and Slave Mode Operation, below).
ADCLRC can also be configured as a GPIO pin. In this case, the ADC will use DACLRC as a frame
clock. The ADCLRC/GPIO1 pin function should not be modified while the ADC is enabled.
DACDAT, DACLRC and BCLK functions can also be supported using GPIO pins. An inverted
ADCLRC can also be output via GPIO pins.
Four different audio data formats are supported:
•
Left justified
•
Right justified
•
I2S
•
DSP mode
All four of these modes are MSB first. They are described in Audio Data Formats, below. Refer to the
“Electrical Characteristics” section for timing information.
Time Division Multiplexing (TDM) is available in all four data format modes. The WM8991 can be
programmed to send and receive data in one of two time slots.
PCM operation is supported using the DSP mode.
MASTER AND SLAVE MODE OPERATION
The WM8991 digital audio interface can operate as a master or slave as shown in Figure 51 and
Figure 52.
Figure 51 Master Mode
Figure 52 Slave Mode
OPERATION WITH ADCLRC AS GPIO
When the ADCLRC/GPIO1 pin is configured as a GPIO pin (ALRCGPIO=1), the DACLRC pin is
used as a frame clock for ADCs and DACs as shown in Figure 53 and Figure 54. The ADCs and
DACs must operate at the same sample rate in this configuration.



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