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WM8991 Datasheet(PDF) 105 Page - Wolfson Microelectronics plc |
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WM8991 Datasheet(HTML) 105 Page - Wolfson Microelectronics plc |
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105 / 174 page  Pre-Production WM8991 w PP, May 2008, Rev 3.1 105 SYSCLK BCLK ADCLRC ADCDAT DACLRC DACDAT BCLK2 DACLRC2 DACDAT2 BCLK Generator ADCLRC Generator DACLRC Generator enable enable enable >1 AIF_MSTR1 ADCLRC_DIR AIF_MSTR1 AIF_MSTR2 0 1 ALRCGPIO1 AIF_SEL >1 AIF_MSTR2 DACLRC_DIR 0 & AIF_SEL 0 1 0 1 AIF_SEL 0 0 1 AIF_SEL & !(ALRCGPIO1 & (ADCENL+ADCENR)) >1 AIF_MSTR1 DACLRC_DIR 0 0 1 DACENL+DACENR 0 1 AIF_SEL & !(ADCENL+ADCENR) 0 Figure 62 Audio Interface Output Control The Audio Interface output control is illustrated above. The master mode control registers AIF_MSTR1 and AIF_MSTR2 as well as the left-right clock control registers ADCLRC_DIR and DACLRC_DIR determine whether the WM8991 generates the according clocks and AIF_SEL and ALRCGPIO1 control registers define the pins these clocks are provided from. |
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