WM8991 datasheet(146/174 Pages) WOLFSON

146 / 174 page

WM8991

Pre-Production

PP, May 2008, Rev 3.1

146

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

8:6

DCLKDIV

[2:0]

111b

Class D Clock Divider

000 = SYSCLK

001 = SYSCLK / 2

010 = SYSCLK / 3

011 = SYSCLK / 4

100 = SYSCLK / 6

101 = SYSCLK / 8

110 = SYSCLK / 12

111 = SYSCLK / 16

Reserved - Do Not Change

4:1

BCLK_DIV

[3:0]

0100b

BCLK Frequency (Master Mode)

0000 = SYSCLK

0001 = SYSCLK / 1.5

0010 = SYSCLK / 2

0011 = SYSCLK / 3

0100 = SYSCLK / 4

0101 = SYSCLK / 5.5

0110 = SYSCLK / 6

0111 = SYSCLK / 8

1000 = SYSCLK / 11

1001 = SYSCLK / 12

1010 = SYSCLK / 16

1011 = SYSCLK / 22

1100 = SYSCLK / 24

1101 = SYSCLK / 32

1110 = SYSCLK / 44

1111 = SYSCL:K / 48

Reserved - Do Not Change

MCLK_SRC

MCLK Source Select

0 = MCLK pin

1 = GPIO2/MCLK2 pin

SYSCLK_SRC

SYSCLK Source Select

0 = MCLK (or MCLK2 if MCLK_SRC=1)

1 = PLL output

CLK_FORCE

Forces Clock Source Selection

0 = Existing SYSCLK source (MCLK, MCLK2 or PLL output)

must be active when changing to a new clock source.

1 = Allows existing MCLK source to be disabled before

changing to a new clock source.

12:11

MCLK_DIV

[1:0]

00b

SYSCLK Pre-divider. Clock source (MCLK, MCLK2 or PLL

output) will be divided by this value to generate SYSCLK.

00 = Divide SYSCLK by 1

01 = Reserved

10 = Divide SYSCLK by 2

11 = Reserved

MCLK_INV

MCLK Invert

0 = Master clock (MCLK or MCLK2) not inverted

1 = Master clock (MCLK or MCLK2) inverted

R07 (07h)

Clocking (2)

9:8

00b

Reserved - Do Not Change

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