HD64F36049 datasheet(412/562 Pages) RENESAS

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Section 19 A/D Converter

Rev. 3.00 Mar. 15, 2006 Page 380 of 526

REJ09B0060-0300

19.3

The A/D converter has the following registers.

• A/D data register A (ADDRA)

• A/D data register B (ADDRB)

• A/D data register C (ADDRC)

• A/D data register D (ADDRD)

• A/D control/status register (ADCSR)

• A/D control register (ADCR)

19.3.1

A/D Data Registers A to D (ADDRA to ADDRD)

There are four 16-bit read-only ADDR registers; ADDRA to ADDRD, used to store the results of

A/D conversion. The ADDR registers, which store a conversion result for each analog input

channel, are shown in table 19.2.

The converted 10-bit data is stored in bits 15 to 6. The lower 6 bits are always read as 0.

The data bus width between the CPU and the A/D converter is 8 bits. The upper byte can be read

directly from the CPU, however the lower byte should be read via a temporary register. The

temporary register contents are transferred from the ADDR when the upper byte data is read.

Therefore, byte access to ADDR should be done by reading the upper byte first then the lower

one. Word access is also possible. ADDR is initialized to H'0000.

Table 19.2

Analog Input Channels and Corresponding ADDR Registers

Analog Input Channel

Group 0

Group 1

A/D Data Register to be Stored Results of A/D Conversion

AN0

AN4

ADDRA

AN1

AN5

ADDRB

AN2

AN6

ADDRC

AN3

AN7

ADDRD

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