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HD64F36049 Datasheet(PDF) 78 Page - Renesas Technology Corp |
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HD64F36049 Datasheet(HTML) 78 Page - Renesas Technology Corp |
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78 / 562 page  Section 3 Exception Handling Rev. 3.00 Mar. 15, 2006 Page 46 of 526 REJ09B0060-0300 Relative Module Exception Sources Vector Number Vector Address Priority Reserved for system use 33 H'000084 to H'000087 High SCI3_3 Receive data full Transmit data empty Transmit end Receive error 34 H'000088 to H'00008B Low Note: * A low-voltage detection interrupt is enabled only in the product with an on-chip power- on reset and low-voltage detection circuit. 3.2 Register Descriptions Interrupts are controlled by the following registers. • Interrupt edge select register 1 (IEGR1) • Interrupt edge select register 2 (IEGR2) • Interrupt enable register 1 (IENR1) • Interrupt enable register 2 (IENR2) • Interrupt flag register 1 (IRR1) • Interrupt flag register 2 (IRR2) • Wakeup interrupt flag register (IWPR) |
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