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HD64F36049 Datasheet(PDF) 16 Page - Renesas Technology Corp

Part # HD64F36049
Description  Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Tiny Series
PDF  562 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HD64F36049 Datasheet(HTML) 16 Page - Renesas Technology Corp

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Rev. 3.00 Mar. 15, 2006 Page xvi of xxxii
16.3.1
PWM Control Register (PWCR) ...................................................................... 296
16.3.2
PWM Data Registers U, L (PWDRU, PWDRL) .............................................. 297
16.4
Operation .......................................................................................................................... 297
Section 17 Serial Communication Interface 3 (SCI3)....................................... 299
17.1
Features............................................................................................................................. 299
17.2
Input/Output Pins.............................................................................................................. 303
17.3
Register Descriptions........................................................................................................ 303
17.3.1
Receive Shift Register (RSR) ........................................................................... 303
17.3.2
Receive Data Register (RDR)........................................................................... 303
17.3.3
Transmit Shift Register (TSR) .......................................................................... 304
17.3.4
Transmit Data Register (TDR).......................................................................... 304
17.3.5
Serial Mode Register (SMR) ............................................................................ 304
17.3.6
Serial Control Register 3 (SCR3) ..................................................................... 306
17.3.7
Serial Status Register (SSR) ............................................................................. 307
17.3.8
Bit Rate Register (BRR) ................................................................................... 309
17.4
Operation in Asynchronous Mode .................................................................................... 318
17.4.1
Clock................................................................................................................. 318
17.4.2
SCI3 Initialization............................................................................................. 319
17.4.3
Data Transmission ............................................................................................ 320
17.4.4
Serial Data Reception ....................................................................................... 322
17.5
Operation in Clocked Synchronous Mode ........................................................................ 326
17.5.1
Clock................................................................................................................. 326
17.5.2
SCI3 Initialization............................................................................................. 326
17.5.3
Serial Data Transmission .................................................................................. 327
17.5.4
Serial Data Reception (Clocked Synchronous Mode) ...................................... 329
17.5.5
Simultaneous Serial Data Transmission and Reception.................................... 331
17.6
Multiprocessor Communication Function ........................................................................ 332
17.6.1
Multiprocessor Serial Data Transmission ......................................................... 334
17.6.2
Multiprocessor Serial Data Reception .............................................................. 335
17.7
Interrupt Requests ............................................................................................................. 338
17.8
Usage Notes ...................................................................................................................... 339
17.8.1
Break Detection and Processing ....................................................................... 339
17.8.2
Mark State and Break Sending ......................................................................... 339
17.8.3
Receive Error Flags and Transmit Operations
(Clocked Synchronous Mode Only).................................................................. 339
17.8.4
Receive Data Sampling Timing and Reception Margin in Asynchronous
Mode ................................................................................................................. 340



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