HD64F36049 datasheet(96/562 Pages) RENESAS

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Section 4 Address Break

Rev. 3.00 Mar. 15, 2006 Page 64 of 526

REJ09B0060-0300

4.1

The address break has the following registers.

• Address break control register (ABRKCR)

• Address break status register (ABRKSR)

• Break address registers E, H, L (BARE, BARH, BARL)

• Break data register (BDRH, BDRL)

4.1.1

Address Break Control Register (ABRKCR)

ABRKCR sets address break conditions.

Bit

Bit Name

Initial

Value

R/W

Description

RTINTE

R/W

RTE Interrupt Enable

When this bit is 0, the interrupt immediately after

executing RTE is masked and then one instruction must

be executed. When this bit is 1, the interrupt is not

masked.

CSEL1

CSEL0

R/W

Condition Select 1 and 0

These bits set address break conditions.

00: Instruction execution cycle

01: CPU data read cycle

10: CPU data write cycle

11: CPU data read/write cycle

ACMP2

ACMP1

ACMP0

R/W

Address Compare 2 to 0

These bits set the comparison condition between the

address set in BAR and the internal address bus.

000: Compares 24-bit addresses

001: Compares upper 20-bit addresses

010: Compares upper 16-bit addresses

011: Compares upper 12-bit addresses

1xx: Reserved

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