HD64F36049 datasheet(9/562 Pages) RENESAS

9 / 562 page

Rev. 3.00 Mar. 15, 2006 Page ix of xxxii

Contents

Section 1 Overview................................................................................................1

1.1

Features................................................................................................................................. 1

1.2

Internal Block Diagram......................................................................................................... 3

1.3

Pin Arrangement ................................................................................................................... 4

1.4

Pin Functions ........................................................................................................................ 5

Section 2 CPU........................................................................................................9

2.1

Address Space and Memory Map ....................................................................................... 10

2.2

Register Configuration........................................................................................................ 11

2.2.1

General Registers ................................................................................................ 12

2.2.2

Program Counter (PC) ........................................................................................ 13

2.2.3

Condition-Code Register (CCR)......................................................................... 13

2.3

Data Formats....................................................................................................................... 15

2.3.1

General Register Data Formats ........................................................................... 15

2.3.2

Memory Data Formats ........................................................................................ 17

2.4

Instruction Set ..................................................................................................................... 18

2.4.1

List of Instructions Classified by Function ......................................................... 18

2.4.2

Basic Instruction Formats ................................................................................... 27

2.5

Addressing Modes and Effective Address Calculation....................................................... 28

2.5.1

Addressing Modes .............................................................................................. 28

2.5.2

Effective Address Calculation ............................................................................ 31

2.6

Basic Bus Cycle .................................................................................................................. 33

2.6.1

Access to On-Chip Memory (RAM, ROM)........................................................ 33

2.6.2

On-Chip Peripheral Modules .............................................................................. 34

2.7

CPU States .......................................................................................................................... 35

2.8

Usage Notes ........................................................................................................................ 36

2.8.1

Notes on Data Access to Empty Areas ............................................................... 36

2.8.2

EEPMOV Instruction.......................................................................................... 36

2.8.3

Bit Manipulation Instruction............................................................................... 37

Section 3 Exception Handling .............................................................................43

3.1

Exception Sources and Vector Address .............................................................................. 44

3.2

Register Descriptions .......................................................................................................... 46

3.2.1

Interrupt Edge Select Register 1 (IEGR1) .......................................................... 47

3.2.2

Interrupt Edge Select Register 2 (IEGR2) .......................................................... 48

3.2.3

Interrupt Enable Register 1 (IENR1) .................................................................. 49

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