HD64F36049 datasheet(58/562 Pages) RENESAS

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Section 2 CPU

Rev. 3.00 Mar. 15, 2006 Page 26 of 526

REJ09B0060-0300

Table 2.8

System Control Instructions

Instruction

Size* Function

TRAPA

—

Starts trap-instruction exception handling.

RTE

—

Returns from an exception-handling routine.

SLEEP

—

Causes a transition to a power-down state.

LDC

B/W

(EAs)

→ CCR

Moves the source operand contents to the CCR. The CCR size is one byte,

but in transfer from memory, data is read by word access.

STC

B/W

CCR

→ (EAd)

Transfers the CCR contents to a destination location. The condition code

access.

ANDC

CCR

∧ #IMM → CCR

Logically ANDs the CCR with immediate data.

ORC

CCR

∨ #IMM → CCR

Logically ORs the CCR with immediate data.

XORC

CCR

⊕ #IMM → CCR

Logically XORs the CCR with immediate data.

NOP

—

PC + 2

→ PC

Only increments the program counter.

Note:

Refers to the operand size.

B: Byte

W: Word

Table 2.9

Block Data Transfer Instructions

Instruction

Size

Function

EEPMOV.B

—

if R4L

≠ 0 then

Repeat @ER5+

→ @ER6+,

R4L–1

→ R4L

Until R4L = 0

else next;

EEPMOV.W

—

if R4

≠ 0 then

Repeat @ER5+

→ @ER6+,

R4–1

→ R4

Until R4 = 0

else next;

Transfers a data block. Starting from the address set in ER5, transfers data

for the number of bytes set in R4L or R4 to the address location set in ER6.

Execution of the next instruction begins as soon as the transfer is

completed.

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