HD64F36049 datasheet(82/562 Pages) RENESAS

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Section 3 Exception Handling

Rev. 3.00 Mar. 15, 2006 Page 50 of 526

REJ09B0060-0300

3.2.4

Interrupt Enable Register 2 (IENR2)

IENR2 enables, timer B1 overflow interrupts.

Bit

Bit Name

Initial

Value

R/W

Description



Reserved

These bits are always read as 0.

IENTB1

R/W

Timer B1 Interrupt Enable

When this bit is set to 1, timer B1 overflow interrupt

requests are enabled.



Reserved

These bits are always read as 1.

When disabling interrupts by clearing bits in an interrupt enable register, or when clearing bits in

an interrupt flag register, always do so while interrupts are masked (I = 1). If the above clear

operations are performed while I = 0, and as a result a conflict arises between the clear instruction

and an interrupt request, exception handling for the interrupt will be executed after the clear

instruction has been executed.

3.2.5

Interrupt Flag Register 1 (IRR1)

IRR1 is a status flag register for direct transition interrupts, RTC interrupts, and

IRQ3 to IRQ0

interrupt requests.

Bit

Bit Name

Initial

Value

R/W

Description

IRRDT

R/W

Direct Transfer Interrupt Request Flag

[Setting condition]

When a direct transfer is made by executing a SLEEP

instruction while DTON in SYSCR2 is set to 1.

[Clearing condition]

When IRRDT is cleared by writing 0

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